1. Field of the Invention
The present invention generally relates to inter-processor communication in a multi-processor (MP) computer system and, more particularly, to an implementation of interrupts directed to a specific processor by its peers in the system.
2. Description of the Prior Art
High performance, MP computer systems are being developed to increase throughput by performing in parallel those operations which can run concurrently on separate processors. Such high performance, MP computer systems are characterized by multiple central processor (CPs) operating independently and in parallel, but occasionally communicating with one another or with a shared memory storage (MS) (i.e., a memory that can be read from and written into by all of the processors) when data needs to be exchanged.
Specific examples of prior art multi-processor systems are shown, for example, in U.S. Pat. No. 3,528,061 to Zurcher, Jr. and U.S. Pat. No. 3,528,062 to Lehman et al. Zurcher, Jr. discloses a multi-processor environment which regulates access to shared memory and allows a processor to lock the memory location for exclusive use. Lehman et al. discloses a multi-processor shared memory system. The Lehman et al. system has storage means accessible to each of the processors wherein different combinations of bits are used to communicate the status of the shared memory.
Communication between processors in a multi-processor system can be accomplished via a shared memory location having a particular address in the MS. Each processor is assigned a distinct memory location whose address is its "interrupt address". The memory location of each interrupt address which may be written to by all processors in the system. When a non-zero value is written into the location at a processor interrupt address, an interrupt is generated for that processor causing it to alter its sequence of instruction execution in a known and organized manner. Such inter-processor interrupts directed to a specific processor by its peers are considered a necessary means of implementing communication and synchronization in a multi-processor configuration. There are, however, several problems associated with MP interrupt handling. Specifically, if memory access is granted on a first-come-first-serve basis, a processor will see only the identity of the last processor that generated an interrupt for it. The problem is to provide a way to guarantee that the interrupted processor will be able to unambiguously identify all processors that interrupt it, even when the interrupts come in quick succession.